ASIC Verification Engineer
Plasma International • Leutershausen, Bavaria, Germany
Role & seniority: Experienced ASIC Verification Engineer (senior-level, global/enterprise context)
Stack/tools: UVM; Specman e; formal verification; directed testing; RTL/gate-level/SystemC; verification toolchains; exposure to power-aware methods (UPF) and basic Python (nice-to-have)
Top 3 responsibilities
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Define and execute advanced verification strategies for complex ASIC developments
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Develop/maintain UVM-based verification environments; perform formal verification and directed testing
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Collaborate with design/system/architecture teams; drive coverage closure and debug RTL/gate-level issues; contribute to methodology improvements
Must-have skills
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Deep ASIC verification expertise (UVM, formal verification, directed testing)
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Strong hands-on experience with Specman e
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Solid understanding of ASIC design process, RTL/gate-level/SystemC, and verification toolchains
Nice-to-haves
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Object-oriented software design concepts
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Python scripting
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Power-aware simulation (UPF)
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Functional safety concepts/standards
Location & work type
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Location not specified
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Work type: Full-time (Vollzeit) in a global semiconductor/engineering context
Full Description
A leading global technology organisation within the semiconductor sector is expanding its ASIC engineering capability. We are seeking an experienced ASIC Verification Engineer to take a central role in verifying complex mixed-signal and digital ASIC platforms.
This position offers the opportunity to work on advanced silicon designs within a highly skilled, international engineering environment.
Key Responsibilities Define and execute advanced verification strategies for complex ASIC developments Develop, maintain, and enhance UVM-based verification environments Perform formal verification and directed testing to ensure design integrity and robustness Collaborate closely with design, system, and architecture teams across the full ASIC lifecycle Drive coverage closure and debug issues at RTL and gate-level abstraction Contribute to the ongoing improvement of verification methodologies, flows, and best practices
Must-Have Experience Deep expertise in ASIC verification methodologies including UVM, formal verification, and directed testing Strong hands-on experience using Specman e as a verification language Solid understanding of the ASIC design process and digital design methodologies Proven track record verifying ASICs using advanced verification and simulation toolchains Good working knowledge of design abstractions including RTL, gate-level, and SystemC
Nice to Have Basic understanding of object-oriented software design principles Experience with scripting languages such as Python Knowledge of power-aware simulation methodologies (e.g. UPF) Familiarity with functional safety concepts and standards
Why Apply Work on technically complex and challenging ASIC developments Join a highly capable, innovation-driven engineering culture Long-term career development within a global semiconductor organisation
For a confidential discussion or to learn more, please get in touch directly.
Karrierestufe Management Beschäftigungsverhältnis Vollzeit Tätigkeitsbereich Ingenieurwesen und Design Branchen Herstellung von Halbleitern, Herstellung von Computern und Elektronik und Herstellung von Haushalts-, Elektro- und Elektronikgeräten
