Design Verification Engineer
VidPro Tech & Hr Solutions Private Limited • Bengaluru, Karnataka, India
Role & seniority
- Technical Engineer (Senior/5–10 years experience in IP core verification)
Stack/tools
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SystemVerilog/UVM HVL, Verilog (HDL)
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DDR protocol verification, BIST understanding (nice to have)
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Test planning, testbench/test case coding, debugging, regression management
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Scripting: Shell, Perl, Python
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DesignWare IP cores, metric collection (functional/Code coverage)
Top 3 responsibilities
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Specify, design/architect and implement state-of-the-art verification environments for DesignWare synthesizable cores; perform IP core verification
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Collaborate with Verification lead and global team; handle test planning, environment coding at IP level, test case coding, debugging, FC coding and review, and regression/quality metric goals
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Study and improve coverage metrics; define additional directed test cases for medium-complexity protocol features; contribute to verification tasks (coverage, debug, regressions) using up-to-date methodologies (UVM)
Must-have skills
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BS/MS in EE/EC; 5+ years in IP core verification
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Proven SystemVerilog/UVM-based test environment development; test plans; functional and code coverage
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DDR protocol experience
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Verilog HDL and scripting (Shell/Perl/Python); strong debugging and problem-solving; good communication; mentoring mindset; self-motivated
Nice-to-haves
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BIST understanding
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Autonomous delivery of deliverables without close supervision
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Experience across distributed, multi-site teams
Location & work type
- Bangalore, I
Full Description
Location: Bangalore
Experience: 5 - 10 Years
Work Mode: 5 Days Work from Office
Role and Responsibilities
He/she will be expected to specify, design/architect and implement state-of-the-art Verification environments for the Design Ware family of synthesizable cores and perform Verification tasks for the IP cores. Has to work closely with Verification lead and be part of a global team of experienced Verification Engineers. The job role will have a combination of Test planning, Test environment coding both at IP level, Test case coding and debugging, FC coding and review and meeting quality metric goals and regression management.
Key Qualification
BS/MS in EE/EC with 5+ years of relevant experience in the verification of IP cores. Must have proven experience in developing HVL (System Verilog/UVM) based test environments, developing and implementing test plans, implementing and extracting verification metrics such as functional coverage and Code coverage. Experience on DDR Protocol is necessary. Understanding of BIST would be an added advantage. Familiarity with HDLs such as Verilog and scripting languages such as shell/Perl/Python etc. is highly desirable. Good communication skills, debug and problem-solving skills, mentoring teammates and should be self-motivated.
Preferred Experience
Be a technical contributor in the Verification Tasks – System Verilog/Verilog coding of testbenches, Test cases, performing verification tasks such as coverage, debug, regressions using the latest methodologies such as UVM. Creates deliverables which do not require close review or supervision by a Senior.
Technical Engineer
Be able to study the coverage metrics and improve them with definition of additional test cases in a directed environment, at least for sayoumall/ medium complexity features of the protocol/ product specs. Works in a project and team-oriented environment with teams spread across multiple sites, worldwide.
Skills: art,design engineering,system verilog,verification,design,case,verilog,metrics,test cases,universal verification methodology (uvm),skills,bist,ip,ddr,hdl,protocol
