FPGA Design & Verification Engineer M/F (H/F) - SAFRAN ELECTRONICS & DEFENSE SERVICES INDIA
AEROCONTACT • Bengaluru, Karnataka, India
Role & seniority: Associate Engineer (FPGA Design and Verification Engineer, Actuation Systems)
Stack/tools: FPGA/ASIC design; VHDL/Verilog; UVM testbench; DO-254 life cycle; RTL simulation (QuestaSim/ModelSim/VCS); SystemVerilog basics; DOORS/Jama for requirements; scripting (Python/Perl/Shell); protocols: PCIe, SPI, ARINC 429, MIL-STD-1553
Top 3 responsibilities
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Develop RTL modules for FPGA/ASIC targets and implement them per guidelines
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Create and maintain testbenches, run simulations, and verify functional requirements with coverage
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Contribute to verification plans, debug RTL/environment issues, and ensure DO-254 compliance
Must-have skills
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Engineering degree (ECE/VLSI) with 13+ years in FPGA/ASIC design or verification
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Proficiency in VHDL or Verilog
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Experience with RTL verification and simulation tools (QuestaSim/ModelSim/VCS)
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Foundational SystemVerilog and UVM knowledge
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Basic scripting (Python/Perl/Shell) for automation
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Familiarity with DO-254 process standards
Nice-to-haves
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Experience with safety-critical hardware development and DO-254 artifacts
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Proficiency with DOORS or Jama for requirements management
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Exposure to ARINC 429, MIL-STD-1553, PCIe, or related aerospace protocols
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Strong problem-solving and cross-team collaboration
Location & work type: Localisation non précisée; type de travail non spécifié (probablement temps plein).
Full Description
Safran est un groupe international de haute technologie opérant dans les domaines de l'aéronautique (propulsion, équipements et intérieurs), de l'espace et de la défense. Sa mission : contribuer durablement à un monde plus sûr, où le transport aérien devient toujours plus respectueux de l'environnement, plus confortable et plus accessible. Implanté sur tous les continents, le Groupe emploie 100 000 collaborateurs pour un chiffre d'affaires de 27,3 milliards d'euros en 2024, et occupe, seul ou en partenariat, des positions de premier plan mondial ou européen sur ses marchés. Safran est la 2ème entreprise du secteur aéronautique et défense du classement « World's Best Companies 2024 » du magazine TIME. Safran Electronics & Defense propose à ses clients des solutions d'intelligence embarquée leur permettant d'appréhender l'environnement, de réduire la charge mentale et de garantir une trajectoire, même en situation critique, ce dans tous les environnements : sur terre, en mer, dans le ciel ou l'espace. La société met les expertises de ses 13 000 collaborateurs au service de ces trois fonctions : observer, décider et guider, pour les marchés civils et militaires.
Descriptif mission
Description of the Role: In this role as an Associate Engineer (FPGA Design and Verification Engineer, Actuation Systems) actively contribute towards architectural design and RTL implementation, while supporting the full verification lifecycle, in accordance with DO-254 process. FPGA JD: Primary Responsibilities: 1.Develop RTL modules using VHDL for FPGA/ASIC targets, following established design guidelines. 2.Develop and maintain testbench components (drivers, monitors, scoreboards) within a UVM (Universal Verification Methodology) environment. 3.Write and execute test cases based on defined test plans to verify functional requirements. 4.Work on industry-standard protocols such as PCIe, SPI, ARINC 429, or MIL-STD-1553. 5.Collaborate with the design team to identify, debug, and resolve RTL bugs and environment issues. 6.Run simulations to collect code and functional coverage; identify and fill coverage gaps to meet project milestones. 7.Assist in the creation of verification plans and design descriptions using requirement management tools like DOORS or Jama. 8.Follow DO-254 process standards for safety-critical hardware development.
Qualifications: Bachelor's/Master's degree in Engineering (ECE , VLSI) 13 years of industry experience in FPGA/ASIC design or verification. Proficiency in hardware description languages (VHDL or Verilog). Familiarity with simulation tools such as QuestaSim, ModelSim, or VCS. Foundational knowledge of SystemVerilog and the UVM framework. Basic scripting skills (Python, Perl, or Shell) for automation. Strong analytical mindset, eager to learn new protocols, and excellent communication skills for team-based problem solving.
