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TPI Global Solutions • Austin, Texas, United States
Role & seniority
Stack / tools
Storage hardware/IP: UFS, NAND, NOR, ePROM; encryption tech preferred
SoC and computer architecture; southbridge tech
Lab equipment, analyzers, hardware debugging; FPGA/pre-silicon emulation
Peripherals: PCIe, NVMe, USB, I2C, UFS, SATA, SPI, UART
Software: BIOS/OS (Windows/Linux), driver interactions; Verilog; Python/C/C++
UFS analyzer/exerciser; test planning tools
Top 3 responsibilities
Lead validation strategies across pre-silicon to post-silicon phases, including software integration
Define tests, enablement, and unit test plans; publish test plan requirements and deliverables
Collaborate across Design, Software, Tools to drive testing/debug methodologies; isolate and debug southbridge/peripheral issues during bring-up, validation, and production
Must-have skills
Deep knowledge of UFS standard/architecture; encryption tech preferred
Strong understanding of SOC architecture and southbridge concepts
Experience with FPGA/ hardware emulation for pre-silicon debug
BIOS/OS and driver-level interactions; common failure modes; boot flows
System peripherals: PCIe, NVMe, USB, I2C, UFS, SATA, SPI, UART
Experience with UFS analyzer/exerciser; lab equipment; hardware networks
Nice-to-haves
3–6 years in pre/post-silicon validation; 4–8 years in semiconductor industry
Hardware description languages (Verilog)
Strong programming/scripting (Python, C/C++, Ruby)
IP/System
Title: UFS IP Validation Engineer
Location: Austin, TX - Onsite
Duration: 12 Months (Possible to extension)
Hardware IP knowledge of storage devices including UFS, NAND, NOR, ePROM, etc
SoC and Computer architecture
Lab equipment, analyzers and hardware debugging techniques.
This role specifically focuses on the validation of external UFS storage devices and bus interconnect, according to the industry standard UFS specification.
Participate in systems design development throughout entire product lifecycle, from pre-silicon and emulation through post-silicon and software integration and validation.
Lead technical presentations, demonstrating a good understanding of hardware architecture and expertise in systems design
Collaborate with Design, Software, Tools and other teams to drive the definition of testing and debug methodologies to provide the best possible coverage and customer experience for the *** UFS IP.
Isolation and debug of issues found in the southbridge and peripherals during pre-silicon, bring-up, validation, and production phases of S3 products.
Defining and executing validation strategies, enablement of features and unit test plans
Publishing and aligning test plan requirements, deliverables and dependencies
Knowledge of UFS standard and architecture, with encryption technology preferred
In-depth knowledge of SOC architecture and concepts
In-depth knowledge of southbridge technology
Experience with FPGA and other hardware emulation platforms for pre-silicon debug
Strong understanding of BIOS, OS (Windows/Linux), and driver-level interactions and common failure points
Good understanding of Boot Flows/Sequences
In-depth knowledge of system peripherals such as PCIe, NVMe, USB, I2C, UFS, SATA, SPI,UART and other data bus connections
Experience with the UFS analyzer/exerciser, common lab equipment, computer hardware, and networks.
Minimum 3-6 years of experience in pre and post-silicon validation and 4-8 years experience in semiconductor industry.
Hardware description languages (e.g. Verilog)
Strong programming/scripting skills (e.g. Python, C/C++, Ruby)
Experience with IP/System level bring-up, SOC debug techniques and methodologies.