Role & seniority: Mid-Senior level; Contract; Engineering (Semiconductor Manufacturing)

Stack/tools: UFS host IP in SoC; storage devices (UFS, NAND, NOR, ePROM); SoC/computer architecture; lab equipment and hardware debugging; FPGA and other pre-silicon emulation; UFS analyzer/exerciser; BIOS/OS/driver interactions; common peripherals (PCIe, NVMe, USB, I2C, UFS, SATA, SPI, UART); basic scripting (Python, C/C++); Verilog (preferred)

Top 3 responsibilities

Define and execute validation strategies and test plans for external UFS storage devices and bus interconnect across pre-silicon to post-silicon/v software integration
Lead technical presentations; collaborate with Design, Software, Tools, Diagnostics, BIOS/Driver teams; drive testing coverage and customer experience
Isolation, debug, and mentoring across southbridge/peripherals during bring-up, validation, and production; identify risks and coordinate mitigations

Must-have skills

Hardware validation experience on UFS host IP in an SoC setting
Hardware IP knowledge of storage devices (UFS, NAND, NOR, ePROM)
SoC and computer architecture; southbridge technology
Lab equipment, analyzers, and hardware debugging techniques
FPGA/emulation for pre-silicon debug; BIOS/OS/driver interactions; boot flows
Experience with peripherals (PCIe, NVMe, USB, I2C, UFS, SATA, SPI, UART); UFS analyzer/exerciser

Nice-to-haves

Encryption knowledge; Verilog; strong programming/scripting (Py

Full Description

Alternate work location can be Austin, Texas

MUST HAVE SKILLS

Hardware Validation experience on the UFS host IP in an SoC setting.
Hardware IP knowledge of storage devices including UFS, NAND, NOR, ePROM, etc
SoC and Computer architecture
Lab equipment, analyzers and hardware debugging techniques

This role specifically focuses on the validation of external UFS storage devices and bus interconnect, according to the industry standard UFS specification.

KEY RESPONSIBILITIES

Participate in systems design development throughout entire product lifecycle, from pre-silicon and emulation through post-silicon and software integration and validation.
Lead technical presentations, demonstrating a good understanding of hardware architecture and expertise in systems design
Collaborate with Design, Software, Tools and other teams to drive the definition of testing and debug methodologies to provide the best possible coverage and customer experience for the UFS IP.
Work with Program Leadership team to define the end to end plan and highlight possible risk areas and address concerns during planning.
Be a leader and mentor to the operation team; be hands-on and lead by example
Isolation and debug of issues found in the southbridge and peripherals during pre-silicon, bring-up, validation, and production phases of S3 products
Able to proactively support team culture that fosters knowledge sharing, excellence, and collaboration
Defining and executing validation strategies, enablement of features and unit test plans
Publishing and aligning test plan requirements, deliverables and dependencies
Working closely with supporting teams such as design, diagnostics, Software/Firmware/BIOS/driver, and project leadership

REQUIREMENTS

Knowledge of UFS standard and architecture, with encryption technology preferred
In-depth knowledge of SOC architecture and concepts
In-depth knowledge of southbridge technology
Experience with FPGA and other hardware emulation platforms for pre-silicon debug
Strong understanding of BIOS, OS (Windows/Linux), and driver-level interactions and common failure points
Good understanding of Boot Flows/Sequences

UFS IP Validation Engineer