
UFS IP Validation Engineer
Infobahn Softworld Inc โข Santa Clara, California, United States
Role & seniority: Mid-Senior level; Contract; Engineering (Semiconductor Manufacturing)
Stack/tools: UFS host IP in SoC; storage devices (UFS, NAND, NOR, ePROM); SoC/computer architecture; lab equipment and hardware debugging; FPGA and other pre-silicon emulation; UFS analyzer/exerciser; BIOS/OS/driver interactions; common peripherals (PCIe, NVMe, USB, I2C, UFS, SATA, SPI, UART); basic scripting (Python, C/C++); Verilog (preferred)
Top 3 responsibilities
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Define and execute validation strategies and test plans for external UFS storage devices and bus interconnect across pre-silicon to post-silicon/v software integration
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Lead technical presentations; collaborate with Design, Software, Tools, Diagnostics, BIOS/Driver teams; drive testing coverage and customer experience
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Isolation, debug, and mentoring across southbridge/peripherals during bring-up, validation, and production; identify risks and coordinate mitigations
Must-have skills
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Hardware validation experience on UFS host IP in an SoC setting
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Hardware IP knowledge of storage devices (UFS, NAND, NOR, ePROM)
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SoC and computer architecture; southbridge technology
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Lab equipment, analyzers, and hardware debugging techniques
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FPGA/emulation for pre-silicon debug; BIOS/OS/driver interactions; boot flows
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Experience with peripherals (PCIe, NVMe, USB, I2C, UFS, SATA, SPI, UART); UFS analyzer/exerciser
Nice-to-haves
- Encryption knowledge; Verilog; strong programming/scripting (Py
Full Description
Alternate work location can be Austin, Texas
MUST HAVE SKILLS
- Hardware Validation experience on the UFS host IP in an SoC setting.
- Hardware IP knowledge of storage devices including UFS, NAND, NOR, ePROM, etc
- SoC and Computer architecture
- Lab equipment, analyzers and hardware debugging techniques
This role specifically focuses on the validation of external UFS storage devices and bus interconnect, according to the industry standard UFS specification.
KEY RESPONSIBILITIES
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Participate in systems design development throughout entire product lifecycle, from pre-silicon and emulation through post-silicon and software integration and validation.
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Lead technical presentations, demonstrating a good understanding of hardware architecture and expertise in systems design
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Collaborate with Design, Software, Tools and other teams to drive the definition of testing and debug methodologies to provide the best possible coverage and customer experience for the UFS IP.
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Work with Program Leadership team to define the end to end plan and highlight possible risk areas and address concerns during planning.
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Be a leader and mentor to the operation team; be hands-on and lead by example
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Isolation and debug of issues found in the southbridge and peripherals during pre-silicon, bring-up, validation, and production phases of S3 products
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Able to proactively support team culture that fosters knowledge sharing, excellence, and collaboration
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Defining and executing validation strategies, enablement of features and unit test plans
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Publishing and aligning test plan requirements, deliverables and dependencies
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Working closely with supporting teams such as design, diagnostics, Software/Firmware/BIOS/driver, and project leadership
REQUIREMENTS
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Knowledge of UFS standard and architecture, with encryption technology preferred
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In-depth knowledge of SOC architecture and concepts
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In-depth knowledge of southbridge technology
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Experience with FPGA and other hardware emulation platforms for pre-silicon debug
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Strong understanding of BIOS, OS (Windows/Linux), and driver-level interactions and common failure points
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Good understanding of Boot Flows/Sequences
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In-depth knowledge of system peripherals such as PCIe, NVMe, USB, I2C, UFS, SATA, SPI,UART and other data bus connections
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Experience with the UFS analyzer/exerciser, common lab equipment, computer hardware, and networks
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Led process improvement initiatives to improve engineering quality
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Strong technical leadership and mentoring skills
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Knowledge of standard power management features and use-cases
PREFERRED EXPERIENCE
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Minimum 3-6 years of experience in pre and post-silicon validation and 4-8 years experience in semiconductor industry
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Hardware description languages (e.g. Verilog)
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Strong programming/scripting skills (e.g. Python, C/C++, Ruby)
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Experience with IP/System level bring-up, SOC debug techniques and methodologies
Seniority level Mid-Senior level Employment type Contract Job function Engineering Industries Semiconductor Manufacturing