Role & seniority: Emulation and Prototyping Engineer, mid-level (3-4 years experience)

Stack/tools: FPGA/emulation platforms (Synopsys HAPS, Protium, Palladium), RTL design (Verilog/SystemVerilog), debugging tools (Verdi, fsdb), scripting (Python, Perl, Tcl, Make/CMake, Shell), SoC buses/protocols (AXI, ACE, APB, PCIe, DDR, Ethernet, SerDes)

Top 3 responsibilities

Build and debug hardware emulation models; import RTL and apply RTL patches for non-synthesis issues; compile and validate emulation models
Perform pre-silicon verification/validation and emulation to ensure functional correctness and performance; partition large SoC RTL for multi-FPGA platforms
Develop and maintain HAPS/FPGA build infrastructure (scripts, flows, makefiles); integrate transactors, high-speed interfaces, and debug instrumentation

Must-have skills

FPGA/RTL experience with SystemVerilog/Verilog
Exposure to emulation/prototyping platforms (HAPS/Zebu, Protium/Palladium)
Strong debugging and RTL bring-up skills; experience with RTL debugging tools (Verdi, fsdb)
Familiarity with ASIC design flows (emulation, verification, bring-up)
Scripting/automation proficiency (Python, Perl, Tcl, Make/CMake, Shell)

Nice-to-haves

Experience with SoC buses/protocols beyond basics (e.g., PCIe, SerDes links)
Experience with large multi-FPGA partitioning and build automation beyond the listed stacks
Exposure to N-1 silicon concepts and pre-to-post-silicon initiative

Full Description

One of our direct clients is looking for an Emulation and Prototyping Engineer. This is a Hybrid opportunity (3 days in Office; Tue, Wed, Thu).

Must Have Skills

FPGA Design Experience
RTL Design using Verilog/System Verilog
Exposure to any Emulation or Prototyping Platform (HAPS/Zebu, Protium/Palladium)

Job Duties

In this position, the engineer will have the following key responsibilities: Hardware emulation model creation. Importing design RTL. Provide RTL patches to address non-synthesis issues. Compile emulation model. Debugging issues found during the process, bring-up, validation, and production phases of SoC programs. Perform pre-silicon verification & validation and emulation to ensure functional correctness and performance. Partition large SoC RTL for multi‑FPGA platforms; develop and maintain HAPS/FPGA build infrastructure including scripts, flows, and makefiles. Integrate custom transactors, high‑speed interfaces, and debug instrumentation. Work with various pre-silicon tools and concepts such as emulation, FPGA, software models, N-1 silicon usage, etc., including pre-to-post-silicon initiatives

Experience

3-4 years of experience on emulation based functional and performance verification for multimillion gate SoC designs.
Should have strong exposure to RTL coding and SOC bring-up.
Hands‑on experience with Synopsys HAPS, Protium, Palladium, or other FPGA/emulation platforms.

Experience with SoC buses and protocols: AXI, ACE, APB, PCIe, DDR, Ethernet, SerDes‑based links, etc. Strong RTL design background using SystemVerilog/Verilog. Good debugging skills, experience of working with various debugging tools on RTL like Verdi, fsdb analysis. Familiarity with ASIC design flows including emulation, verification and bring up.

Expertise in scripting/automation: Python, Perl, Tcl, Make/CMake, Shell.

Verification Consultant (FPGA)