Role & seniority: Verification Engineer (senior level); full-chip/SoC verification focus.

Stack / tools

Languages: ASM, C, C++, Perl, TCL, Python; Verilog/SystemVerilog (nice-to-have)
Emulation/FPGA: ZeBu Server, Palladium, Veloce; EP, HAPS, Protium
Debug/verification: Perspec, Threadmill, OS, drivers; Verdi, Verisium
Other: EDA tools, automation, flow enhancements; RTL-to-Emulation flow understanding

Top 3 responsibilities

Plan, develop, execute, and debug full-chip/SoC verification tests on emulation platforms
Collaborate with design engineers to define verification scenarios and debug tests for functional correctness
Define/drive coverage measures, analyze gaps, and push towards tape-out; reproduce failures with software and post-silicon validation teams

Must-have skills

5+ years in full-chip/SoC verification (test definition, creation, execution, debug)
Experience creating full-chip/SoC tests and debugging on hardware emulation or FPGA
Proficiency in C/C++, Python (and scripting), plus TCL/Perl
Familiarity with design debug tools (Verdi, Verisium)
Understanding of RTL to emulation/FPGA flows and SoC interfaces (CPU, DDR, PCIe, Ethernet)

Nice-to-haves

Verilog/SystemVerilog coding (design)
Embedded software/firmware experience (Linux drivers, validation)
Experience with associated EDA tools, automation, and flow enhancements
Broad SoC architecture knowledge and interconnects
Location & wor

Full Description

MINIMUM QUALIFICATIONS

Bachelor's degree in Computer Science, Electrical Engineering, or equivalent practical experience.
5 year of experience with full-chip/SoC verification (e.g., test definition, creation, execution, and debug).

* Experience developing full-chip/SoC tests using these environments/tools

ASM, C, C++, Perspec, Threadmill, OS, or drivers.
- Experience with execution and RTL/firmware/software debug on hardware
- emulation (e.g., ZeBu Server, Palladium, Veloce) or FPGA (e.g., EP, HAPS,
- Protium).
- Experience with design debug tools (e.g., Verdi, Verisium).
- Experience with coding and scripting in C, C++, Perl, TCL, or Python.

PREFERRED QUALIFICATIONS

Experience with associated EDA tools, automation, and flow enhancements.
Experience with coding in Verilog/SystemVerilog (for design).
Experience in embedded software and firmware (e.g., Linux drivers, firmware validation).
Understanding of RTL to emulation/FPGA flows including emulation test benches (e.g., transactors/accelerated VIPs, hybrid, in-circuit emulation).
Understanding of SoC architecture and interfaces (e.g., CPU, DDR, PCIe, interconnect, Ethernet, etc.).

ABOUT THE JOB

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

RESPONSIBILITIES

Plan and execute the verification of digital design blocks by understanding specifications and working with design engineers to define key verification scenarios.
Develop, execute, and debug full-chip/system on a chip (SoC) tests on emulation platforms.
Collaborate with design engineers to debug tests and ensure functional correctness of design blocks.
Define and implement various coverage measures to capture stimulus and corner-case scenarios. Work with software and post-silicon validation teams to reproduce failures on emulation.
Drive coverage analysis to identify verification gaps and demonstrate progress towards tape-out. Explore new verification and emulation methodologies and implement them.

Senior Emulation Verification Engineer, Google Cloud