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🤖 15+ AI Agents working for you. Find jobs, score and update resumes, cover letter, interview questions, missing keywords, and lots more.
Apple • Cupertino, California, United States
Salary: $156,853 - $220,900 / year
Role & seniority
Stack / tools
SystemVerilog (RTL, testbench, DV code)
Universal Verification Methodology (UVM)
Verdi (debug/tracing)
C/C++ for test code
Verilog for RTL/Testbench
Scripting: Perl, Python
Verification planning, testbench environments, DV IP
Top 3 responsibilities
Engage with design and micro-architecture teams to understand functional/performance objectives; assess specs and identify ambiguities
Establish robust testbench methodology; write tests, generate coverage, and develop SystemVerilog checkers using UVM; update tests for evolving needs
Execute regression tests, analyze failures, trace signals, and collaborate with design to resolve issues; own tasks end-to-end
Must-have skills
Master’s degree (EE, Electronics, or related) or foreign equivalent
Proficiency in SystemVerilog for RTL and testbench development
Experience with C/C++ for SoC test code; Verilog for RTL
Scripting in Perl and Python for automation; DV concepts and RTL verification
Knowledge of computer architecture and SOC/architecture principles; DV planning and functional verification
Nice-to-haves
Location & work type
Cupertino, California and various unanticipated locations across the USA
Full-time, 40 hours/week
Eligible for Apple benefits, stock programs, relocation assistance, and educational reimbursements per policy
Imagine what you can do here. Apple is a place where extraordinary people gather to do their lives best work. Together we create products and experiences people once couldn’t have imagined, and now, can’t imagine living without. It’s the diversity of those people and their ideas that inspires the innovation that runs through everything we do.
DESCRIPTION
APPLE INC has the following available in Cupertino, California and various unanticipated locations throughout the USA. Engage in regular meetings with design and micro architecture teams to comprehend the functional and performance objectives of the ongoing design projects. Thoroughly examine and assess design specifications to gain a comprehensive understanding of the project requirements. Identify potential areas for improvement or clarification. Establish a robust testbench methodology tailored to project requirements, ensuring efficient verification processes. Write Tests and Generate Test Coverage. Develop SystemVerilog checkers using UVM methodology to verify new debug features. Regularly update and enhance test cases to adapt to evolving project needs. Execute regular regression tests to validate the functionality and performance of the design under various scenarios. Analyze test failures, trace signals using tools like Verdi, and collaborate with the design team to address issues. Take ownership of individual tasks and deliverables, ensuring alignment with project goals and timelines. 40 hours/week. At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $156,853- $220,900/yr and your base pay will depend on your skills, qualifications, experience, and location. PAY &
BENEFITS: Apple employees also have the opportunity to become an Apple shareholder through participation in Apple’s discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating
Benefits: https://www.apple.com/careers/us/benefits.html. Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.
MINIMUM QUALIFICATIONS
Master's degree or foreign equivalent in Electrical Engineering, Electronics
Engineering, or a related field. Experience and/or education must include: Using System Verilog for developing and debugging RTL, testbench environment, Models, and Verification IP code Utilizing C++ and C for developing SoC test code Using Verilog to write and debug RTL and Testbench code Scripting using Perl and Python for testbench simulation flows automation Proficiency in Computer Architecture to apply to SOC architecture and design Performing RTL design verification using digital circuits/design concepts Utilizing design verification concepts to functionally verify RTL Design Under Test
PREFERRED QUALIFICATIONS
N/A