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Apple • Cupertino, California, United States
Salary: $128,944 - $190,900 / year
Role & seniority: Verification Engineer (likely mid-senior level) at Apple.
SystemVerilog, SystemVerilog Assertions, UVM
Python, Perl, C/C++
CAD/RTL simulation and test bench development
Verilog test benches, coverage plans, regression management
Design/architecture collaboration, bug tracking
Develop verification plans, test benches, tests, and coverage plans to verify hardware designs; define next-generation verification methodology
Implement tests and assertions; automate verification flows; run simulations and triage regressions at block, subsystem, or chip level
Collaborate with design, DV, architecture, validation, and software teams; track and close defects; analyze coverage and refine tests/constraints
Bachelor’s degree in Electrical Engineering, Computer Science, or related field
Experience with object-oriented design, data structures, algorithms
Proficiency in Verilog for testbenches, SystemVerilog/UVM, Python for automation
C/C++ for firmware understanding; knowledge of digital logic, VLSI, timing/power/area considerations
Ability to develop exhaustive test plans from internal/external design docs; run and debug RTL simulations
Nice-to-haves: N/A
Cupertino, CA, and various unanticipated locations across the USA
40 hours/week; eligibility for relocation; full compensation package including stock programs and benefi
Imagine what you can do here. Apple is a place where extraordinary people gather to do their lives best work. Together we create products and experiences people once couldn’t have imagined, and now, can’t imagine living without. It’s the diversity of those people and their ideas that inspires the innovation that runs through everything we do.
DESCRIPTION
APPLE INC has the following available in Cupertino, and various unanticipated locations throughout the USA. Work closely with design and architecture teams to understand the functional and performance goals of a design and detailed design features to develop effective verification plans. Collaborate with all relevant teams, including design, DV, architecture, validation and software. Work closely with the team, review specifications, develop verification plan, test benches, tests and coverage plans, and execute plans to verify hardware design. Define next generation verification methodology. Implement test benches using System Verilog and UVM. Implement tests in System Verilog, UVM and C per the test plan. Implement assertions in System Verilog Assertion language. Automate verification flows using Python, Perl or other scripting languages. Run simulations on CAD (computer-aided design) software. Create, run and triage regressions of block level, subsystem level or chip level simulations. Track bugs and file bug reports for simulation failures and track them until fix and closure. Analyze coverage and update tests and constraints to close gaps and achieve top results. 40 hours/week. At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $128,944 - $190,900/yr and your base pay will depend on your skills,
qualifications, experience, and location. PAY & BENEFITS: Apple employees also have the opportunity to become an Apple shareholder through participation in Apple’s discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple’s Employee Stock Purchase Plan.
You’ll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses — including tuition. Additionally, this role might be eligible for discretionary bonuses or
https: //www.apple.com/careers/us/benefits.html. Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.
MINIMUM QUALIFICATIONS
Bachelor's degree or foreign equivalent in Electrical Engineering and Computer Sciences, Electrical Engineering, Electronics Engineering, or a related field.
Experience and/or education must include: Using object-oriented programming principles to design and implement a specified functionality. Leveraging data structures, types, and algorithms to develop efficient and scalable code. Utilizing computer architecture, VLSI, and logic design to understand and analyze hardware behavior. Using Verilog to implement testbenches and test cases to verify hardware behavior. Using Python to create and maintain custom scripts and internal tools for automation and reporting. Using C/C++ to understand, develop, and maintain system firmware code. Using Digital Logic Design, interconnect network, cache, and memory architecture to be able to understand internal/external design documentations and RTL code to develop exhaustive test plans. Developing ASIC (Application Specific Integrated Circuits) and using knowledge of Integrated Circuits to understand low level details on logic design including timing, power, and area. Using digital design simulator to run and debug RTL and power aware simulation.
PREFERRED QUALIFICATIONS
N/A