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LeadStack Inc. • San Jose, California, United States
Role & seniority: Senior Staff Engineer, Digital Verification (ACAS)
Hardware verification: SystemVerilog UVM, testbench development, constrained-random and directed test cases
Verification of MCU/CPU: processor and sub-system level, core/micro-architecture verification, multi-processor cache coherency
Coverage: functional coverage modeling; coverage data analysis
Low-power design: testbenches and simulations with Hybrid UPF and PG netlists
Simulation/debug: EDA tools (Synopsys VCS, Cadence Xcelium, Siemens QuestaSim), debugging (Verdi, SimVision)
Programming/scripting: C++, SystemVerilog, Python/Perl
Formal verification familiarity; DMS verification knowledge preferred
Define verification specifications with RTL designers and system architects; design and implement full-chip and block-level test suites
Develop and debug simulations at RTL and gate levels; build and analyze low-power testbenches and coverage models
Manage regression activities; file and track defects using bug-tracking systems; analyze and drive coverage improvements
Bachelor’s degree with 15+ years (or Master’s with 13+; PhD with 10+ preferred) in Electrical Engineering or related field
Extensive SystemVerilog UVM experience; constrained-random and directed test case development
MCU/CPU verification experience at processor and sub-system levels; strong CPU architecture knowledge (x86, ARM, RI
Job Description LeadStack Inc. is an award winning, one of the nation's fastest growing, certified minority owned (MBE) staffing services provider of contingent workforce. As a recognized industry leader in contingent workforce solutions and Certified as a Great Place to Work, we're proud to partner with some of the most admired Fortune 500 brands in the world.
Senior Staff Engineer, Digital Verification - ACAS
Location: San Jose, CA – Onsite
Duration: 6+months
Pay Rate: $90/hr – $100/hr
Vertical: Engineering
Description What You’ll Do Collaborate with RTL Designers and System Architects to define verification specifications. Design test suites for full-chip and block-level verification; develop directed and constrained-random test cases; analyze and debug simulations at RTL and gate levels. Build functional coverage models, collect, and analyze coverage data. Build testbenches for low-power designs; analyze simulations with Hybrid UPF and PG netlists. Manage regression analysis; file and track bugs using bug-tracking systems.
Requirements Bachelor’s degree with 15+ years of relevant industry experience, Master’s with 13+ years, or PhD with 10+ years in Electrical Engineering or related field (preferred). Experience developing testbenches using SystemVerilog UVM, including test case development for constrained-random and directed scenarios. Experience in MCU/CPU verification at both processor and sub-system levels.
Experience with EDA tools: Simulators (Synopsys VCS, Cadence Xcelium, Siemens QuestaSim, or equivalent); debugging tools (Synopsys Verdi, Cadence SimVision).
know more about current opportunities at LeadStack , please visit us on https: //leadstackinc.com/careers/ Should you have any questions, feel free to call me on (513) 3184502 or send an email on waseem.ahmad@leadstackinc.com