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Apple • Texas, United States
Role & seniority: Design Verification Engineer (senior; ~10+ years experience)
Languages/Tech: SystemVerilog, OOP, UVM; scripting (Python, Perl, TCL)
Verification: DV methodology, test plans, scalable portable test-benches; stimulus, checkers, assertions, coverage
Tools: simulators, waveform viewers, build/run automation; coverage tooling; UPF/power-aware verification
Advanced: use of LLMs for efficiency/quality; emulation and formal verification/ gate-level considerations (preferred/optional)
Establish DV methodology, develop verification plans aligned to IP/micro-architecture
Create/maintain verification environment (stimulus, checkers, assertions, trackers) and write tests; debug, measure coverage, drive sign-off for RTL freeze and tape-out
Bring-up DV environment and features, enable regression, track DV progress with metrics; develop block/IP/SoC level test benches
BS in technical field with ~10+ years relevant experience
Deep knowledge of OOP, SystemVerilog, UVM
Experience with scalable/portable test-benches, verification methodologies/tools, simulators, waveform viewers
Build/run automation, coverage collection; debugging and test-plan execution
Proficiency in Python/Perl/TCL; familiarity with IP/SoC-level DV
Ability to work with LLMs to improve efficiency and quality
Knowledge of UPF or power-aware verification (preferred)
At Apple, we work every single day to craft products that enrich people’s lives. Do you love working on challenges that no one has solved yet and changing the game? We have an opportunity for an outstandingly hardworking design verification engineer! As a member of our wide-ranging group, you will have the rare and extraordinary opportunity to craft upcoming products that will delight and encourage millions of Apple’s customers daily. This role is for a DV engineer who will enable us to produce fully functional first silicon for IP designs. The responsibilities include all phases of pre-silicon verification
including but not limited to: establishing DV methodology, test-plan development, verification environment development including stimulus and checkers, test-writing, debug, coverage, sign-off for RTL freeze and tape-out.
DESCRIPTION
In this role, you will be responsible for ensuring bug-free first silicon for part of the SoC / IP and are encouraged to develop detailed test and coverage plans based on the micro-architecture. You are responsible for developing verification methodology suitable for the IP, ensuring a scalable and portable environment. You will get to develop verification environment, including all the respective components such as stimulus, checkers, assertions, trackers, coverage. A mindset to break the design is highly desirable. Furthermore, you will develop verification plans for all features under your care, execute verification plans, including design bring-up, DV environment bring- up, regression enabling features, and debug of the test failures. You will also learn to develop block, IP and SoC level test-benches track and report DV progress using a variety of metrics, including bugs and coverage. You will also be expected to make use of LLM and related technologies to achieve efficient execution and improved quality.
MINIMUM QUALIFICATIONS
BS degree in technical subject area and a minimum 10 years relevant industry experience or equivalent
PREFERRED QUALIFICATIONS
Deep knowledge of OOP, SystemVerilog and UVM Deep knowledge in developing scalable and portable test-benches Strong experience with verification methodologies and tools such as simulators, waveform viewers, Build and run automation, coverage collection, gate level simulations Working experience using LLMs for efficiency and quality Experience with power-aware (UPF) or similar verification methodology Excellent knowledge of one of the scripting languages such as Python, Perl, TCL Experience with serial protocols such as PCIe or USB, parallel protocol such as DDR is a plus but not required Knowledge of formal verification methodology is a plus but not required Knowledge of emulation for verification technologies is a plus but not required