Wireless Radio Verification Engineer
Apple • San Diego, California, United States
Role & seniority: Wireless Radio Verification Engineer (mid-level); BS + ~3+ years in ASIC verification
Stack/tools: SystemVerilog/UVM verification; RTL (Verilog/VHDL); testbench development; Python, Bash/Perl scripting; digital design fundamentals; exposure to RF/analog concepts
Top 3 responsibilities
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Verify radio digital controllers and RF subsystems to ensure first-time silicon success
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Develop verification environments and testbench components for complex radio control paths and operating modes
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Own subsystem verification from test planning through coverage closure, including scenario creation and debugging
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Must-have skills: BS + 3+ years in ASIC verification; SystemVerilog/UVM; RTL simulation; RTL design fundamentals; Python or similar scripting; experience bringing up designs in simulation and debugging functional issues
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Nice-to-haves: Experience with digital controllers/subsystems data paths; constrained random testing, functional coverage, assertion-based verification; mixed-signal modeling; RF/analog exposure (LNA, mixers, PLLs, amplifiers, LDOs, DAC/ADC); additional scripting proficiency (Perl, Bash)
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Location & work type: Not specified in posting; details not disclosed
Full Description
Join Apple's Wireless Connectivity team developing state-of-the-art WiFi SoCs that power hundreds of millions of Apple products worldwide. You'll be part of our vertically integrated organization shaping next-gen wireless technology from concept through production. As a Wireless Radio Verification Engineer, you'll ensure first-time-right silicon success through sophisticated testbenches, comprehensive scenarios, and cutting-edge verification methodologies—enabling multi-gigabit wireless technology connecting the world!
DESCRIPTION
As a Wireless Radio Verification Engineer, you'll verify Radio digital controllers combined with RF subsystems that enable exceptional wireless performance. You'll develop verification environments for complex radio control / transceiver paths spanning PLLs, DAC / ADC data paths, power management, and co-existence mechanisms. This role emphasizes digital verification while bridging to RF/analog domains—you'll work closely with Design, RF, PHY, and Systems teams to understand radio specifications and develop comprehensive test strategies. You'll own subsystem verification from test planning through coverage closure, building testbench components and scenarios that exercise complex radio control sequences and operating modes.
MINIMUM QUALIFICATIONS
BS and a minimum of 3 years of relevant industry experience. Understanding of ASIC verification flows with SystemVerilog including UVM testbench development, scenario creation, and RTL simulation. Experience developing verification environments, bringing up designs in simulation, and debugging functional issues. Experience with digital design fundamentals Verilog or VHDL. Experience with scripting languages such as Python, or similar. Strong problem-solving abilities and collaborative approach to engineering challenges.
PREFERRED QUALIFICATIONS
Experience with digital controllers, subsystems, or data paths. Experience with constrained random testing, functional coverage implementation, UVM methodology, and assertion-based verification. Exposure to mixed-signal modeling concepts including real-number modeling. Exposure to RF/analog system design such as LNAs, Mixers, PLLs, amplifiers, LDOs, DAC / ADCs. Proficiency with Python, Perl, Bash or similar scripting for automation. Great teammate with excellent communication skills and desire to seek diverse technical challenges.
