Role & seniority: Senior/lead verification engineer (block/sub-system and full-chip verification) for Analog Mixed-Signal products.

Stack/tools: SystemVerilog, UVM; RTL/gate simulations; AMS verification (top-level, Spice); analog modeling (Verilog-A); co-simulation with digital/mixed-signal; scripting (Python, Perl, Bash); cocotb is a plus.

Top 3 responsibilities

Architect, develop, and lead verification for complex AMS/ASIC blocks and full-chip verification; define verification plans and architectures.
Create, simulate, debug test benches and scenarios; drive coverage analysis, regressions, and issue tracking; execute test plans to achieve tapeout readiness.
Collaborate with design, systems, and analog teams; support digital + mixed-signal co-simulations; review specs and extract features for verification scope.

Must-have skills

10+ years in ASIC/FPGA verification; Digital DV with robust IP verification experience.
Advanced ASIC verification flows using SystemVerilog and UVM; test bench development from scratch; constrained random testing; coverage closure.
RTL/gate-level simulations; scripting proficiency (Python, Perl, Bash); strong communication and mentoring abilities.

Nice-to-haves

AMS verification exposure; RTL + Spice understanding; Verilog-A modeling; basic analog concepts (KCL, KVL); cocotb-based verification; experience with AC/DC products.
Location & work type: Not specified in the provided text.

Full Description

This role will empower you to lead critical block or sub-system verification and full chip verification of complex Analog mixed signal products.

Your Role

Key responsibilities in your new role

This role will empower you to lead critical block or sub-system verification and full chip verification of complex Analog mixed signal products.
Architect and develop test benches and environments.
You will create, simulate, and debug test scenarios, and lead regressions and issue tracking. There will be collaboration with design and systems engineering teams to review specifications and architecture,extract features, and define verification plans.
You'll drive coverage analysis and closure, and collaborate with /support digital + mixed-signal co-simulations using System Verilog analog behavioral models.
Working closely with Analog team and AMS simulation and verification.
Define verification plan and verification architecture required for verifying required RTL.
Execute Defined test-plans to ensure bug free tapeout.
Develop required verification components.
Test plan execution and debugging of RTL.
Meet verification targets (coverage closure, Regression clean-up).
AMS verification will involve extensive testing of top level AMSsimulation ( RTL + Spice).

Your Profile

Qualifications and skills to help you succeed

Bachelors/Master’s degree in Electronics /Electrical Engineering
10+ years of Industry experience
Digital DV
Leadership experience verifying complex IP with a track record of robust ASICs.
Advanced knowledge of ASIC verification flows with System Verilog and UVM.
Experience developing test benches from scratch, bringing up designs in simulation.
Skills with constrained random testing, coverage closure, and RTL /gate simulations.
Proficient in a scripting language such as Python, Perl, Bash orsimilar.
Great teammate / mentor with excellent communication skills and the desire to seek diverse challenges.
Exposure to AMS verification is a Plus and would be given preference
Understanding of RTL + Spice simulation
Willingness to learn basics of analog design
Familarity with VerilogA and other modeling should be help
Basic Analog concepts like KCL, KVL etc.
Exposure to AC2DC or DC2DC products is a great advantage
Willingness to work with analog team for top level AMS verification.
Exposure to cocotb based verification is an added preference.

Senior Staff Engineer Verification