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AMD • Bengaluru, Karnataka, India
Salary: USD 0 per year
Role & seniority
Stack / tools
SystemVerilog, UVM, SystemVerilog Assertions (SVA)
RTL verification, Gate-level sim, Analog Mixed-Signal (AMS) simulations
UPF-based low-power RTL verification
Digital-analog co-simulation (cosims) (desirable)
Coverage: code, functional, and assertion-based; experience with regressions
Top 3 responsibilities
Verify IP features across RTL, gate-level sim, and AMS simulations
Create methodology-based UVM verification testbenches and components from scratch for various IP features
Ensure quality deliverables via regressions and achieve high verification coverage; conduct reviews and provide feedback to design/architecture teams
Must-have skills
13+ years of relevant experience
Expertise in SystemVerilog, UVM-based testbench architectures, and SVA
Strong code and functional coverage expertise
Excellent problem solving, debugging, and communication skills
Strong digital design knowledge
Exposure to UPF low-power RTL verification
Nice-to-haves
Experience leading a team
PLL verification and mixed-signal verification methodologies
Exposure to digital-analog co-simulations (cosims)
Location & work type
Location not specified; work across multiple sites/timezones
Full-time role (implicit from posting)
WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.
SMTS SILICON DESIGN ENGINEER
Verification of IP features: Test plan creation, Verification of the IP in RTL, Gatesim and Analog Mixed Signal simulations. Create methodology-based (UVM) verification testbenches and components from scratch for various IP features. Quality deliverables through regressions
Verification coverage: code-coverage, functional coverage, assertions, to achieve 100% verification completeness Reviews, and feedback to design/architecture teams.
AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.