🤖 15+ AI Agents working for you. Find jobs, score and update resumes, cover letter, interview questions, missing keywords, and lots more.
Cookies & analytics consent
We serve candidates globally, so we only activate Google Tag Manager and other analytics after you opt in. This keeps us aligned with GDPR/UK DPA, ePrivacy, LGPD, and similar rules. Essential features still run without analytics cookies.
Read how we use data in our Privacy Policy and Terms of Service.
🤖 15+ AI Agents working for you. Find jobs, score and update resumes, cover letter, interview questions, missing keywords, and lots more.
Mediatek • 贺费, Yunnan, China
Role & seniority: Verification Engineer (AMS IP Design Verification), mid-level with 1+ years ASIC functional verification experience
Stack/tools: UVM-based verification; Verilog/SystemVerilog/SVA; test bench development; RTL and gate-level simulations; coverage tools; scripting (Unix/Linux shell, Python, Perl, Makefile); revision control (e.g., Perforce, ClearCase)
Develop scalable and portable test benches, test cases, drivers, checkers, assertions, and reference models to meet functional and code coverage goals
Drive DV process from specification to test plan, configurable test bench and test suite development; perform RTL/Gate-level simulations and achieve coverage closure
Collaborate with global architecture/design/verification/post-silicon teams to address DV needs and improve AMS DV processes
Solid knowledge of ASIC design flow, Digital Design, and UVM-based verification
Proficiency in UVM, Verilog/SystemVerilog, and SystemVerilog Assertions (SVA)
Experience with test bench development, simulation, debugging, and coverage closure
1+ years of ASIC functional verification; exposure to analog/mixed-signal or SERDES IPs (e.g., USB, UFS, PCIe, DDR-PHY) is a plus
Power-aware and gate-level simulations
Scripting/automation: Unix/Linux shell, Python, Perl, Makefile; revision control (Perforce, ClearCase)
Knowledge of Analog Mixed-Signal design fundamentals and analog
Job Description
Work in AMS IP Design Verification, in UVM-based verification environment. Work in DV process from specification to test plan, to configurable test bench, drivers and checkers development, to test suite building to meet functional and code coverage goals Apply wide range of Digital and/or AMS DV skills to help and support AMS IP or Chip DV Teams to establish or enhance new or existing DV capabilities, including but not limited to developing scalable and portable Test bench, test cases, drivers, checkers, assertions, and reference models, and running RTL and Gate Level simulations and reaching all coverage closures. Communicate and collaborate with global architecture, design, verification, and post-Silicon testing teams to address new needs or requirement on DV Support. Contribute to continuous improving on AMS DV process for better quality and efficiency through methodology and process improvements.
Requirement
Quick learner with strong critical thinking and creative problem-solving skills. Solid knowledge in ASIC design process, Digital Design and UVM-based design verification methodologies.
Proficient on using design and verification languages: UVM, Verilog, System Verilog, and System Verilog Assertions (SVA). Proficient on Design Verification tools and techniques, including test bench development, simulation, debugging and coverage closure, etc. Knowledge on Design Verification development process, from specification to test plan, to configurable test bench, drivers and checkers development, to test suite building to meet functional and code coverage goals, 1+ years ASIC functional verification hands-on work experience, preferably with some verification experience on analog mixed signal IPs or SERDES IPs, such as USB, UFS, PCIe, DDR-PHY, etc. Power-aware simulations and gate level simulations is a plus
Scripting and automation skills: Unix/Linux shell programming, Perl, Python, Makefile, and revision management (e.g., Perforce, ClearCase, etc.) is a plus. Knowledge of Analog Mixed-Signal Design Fundamentals and analog behavioral modeling is a plus
Familiar with programming languages: C, C++, and/or SystemC is a plus.