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Mediatek • 贺费, Yunnan, China
Role & seniority: ASIC/AMS IP Design Verification Engineer; 1+ year of ASIC functional verification experience (entry to mid-level).
Stack/tools: UVM, Verilog, SystemVerilog, SystemVerilog Assertions (SVA); test bench development, RTL and gate-level simulations, coverage closure; DV tools and techniques; Unix/Linux scripting (Python, Perl, Makefile); revision control (Perforce, ClearCase); (plus: AMS/analog/mixed-signal context).
Develop scalable, portable test benches, test cases, drivers, checkers, and assertions; build test suites to meet functional and code coverage goals.
Execute RTL and gate-level simulations, perform debugging, and drive coverage closure.
Collaborate with global architecture, design, verification, and post-silicon teams; contribute to continuous improvement of AMS DV processes.
1+ year ASIC functional verification experience
Proficiency in UVM, Verilog, SystemVerilog, and SVA
Experience with test bench development, simulation, debugging, and coverage closure
Knowledge of DV development lifecycle (spec to test plan to configurable test bench, drivers/checkers, test suite)
Strong learning, critical thinking, and problem-solving abilities
Analog/mixed-signal IP or SERDES (USB, UFS, PCIe, DDR-PHY) experience
Power-aware and gate-level simulations
Scripting/automation: Unix/Linux shell, Python, Perl, Makefile; experience with Perforce or Cle
Job Description
Work in AMS IP Design Verification, in UVM-based verification environment. Work in DV process from specification to test plan, to configurable test bench, drivers and checkers development, to test suite building to meet functional and code coverage goals Apply wide range of Digital and/or AMS DV skills to help and support AMS IP or Chip DV Teams to establish or enhance new or existing DV capabilities, including but not limited to developing scalable and portable Test bench, test cases, drivers, checkers, assertions, and reference models, and running RTL and Gate Level simulations and reaching all coverage closures. Communicate and collaborate with global architecture, design, verification, and post-Silicon testing teams to address new needs or requirement on DV Support. Contribute to continuous improving on AMS DV process for better quality and efficiency through methodology and process improvements.
Requirement
Quick learner with strong critical thinking and creative problem-solving skills. Solid knowledge in ASIC design process, Digital Design and UVM-based design verification methodologies.
Proficient on using design and verification languages: UVM, Verilog, System Verilog, and System Verilog Assertions (SVA). Proficient on Design Verification tools and techniques, including test bench development, simulation, debugging and coverage closure, etc. Knowledge on Design Verification development process, from specification to test plan, to configurable test bench, drivers and checkers development, to test suite building to meet functional and code coverage goals, 1+ years ASIC functional verification hands-on work experience, preferably with some verification experience on analog mixed signal IPs or SERDES IPs, such as USB, UFS, PCIe, DDR-PHY, etc. Power-aware simulations and gate level simulations is a plus
Scripting and automation skills: Unix/Linux shell programming, Perl, Python, Makefile, and revision management (e.g., Perforce, ClearCase, etc.) is a plus. Knowledge of Analog Mixed-Signal Design Fundamentals and analog behavioral modeling is a plus
Familiar with programming languages: C, C++, and/or SystemC is a plus. Show more Show less