Role & seniority: AMS Functional Verification Engineer (3+ years in ASIC DV); senior levels available for proven expertise.

Stack/tools: UVM-based verification; Verilog/SystemVerilog; SystemVerilog Assertions (SVA); DV/testbench development; RTL and gate-level simulations; coverage tooling; Unix/Linux shell scripting; Python/Perl; Makefile; version control (e.g., Perforce, ClearCase). Familiarity with analog/mixed-signal IPs (SERDES, sensors) and AMS modeling. Helpful: C/C++, SystemC; power-aware simulations.

Top 3 responsibilities

Conduct AMS IP/Chip DV in a UVM environment from specification to test plan, configurable test benches, drivers and checkers, to test suites meeting functional and code coverage goals.
Develop scalable, portable test benches and reference models; execute RTL and gate-level simulations; drive coverage closures.
Collaborate with global architecture, design, verification, and post-silicon teams; contribute to DV process improvements and evolve verification methodologies.

Must-have skills: 3+ years ASIC functional verification experience; strong UVM, Verilog/SystemVerilog, and SVA skills; test bench development, debugging, and coverage closure; understanding of DV lifecycle from spec to test plan and test suite.
Nice-to-haves: Analog/mixed-signal design fundamentals; experience with AMS IPs (e.g., SERDES, USB/UFS/PCIe, DDR-PHY); power-aware and gate-level simulations; scripting (Python, Perl, Unix shell); Makefil

Full Description

Job Function

Work on Analog/Mixed-Signal Functional Verification for Analog/Mixed-Signal IPs, such as SERDES, Sensors and beyond. The candidate will work with digital design, analog design, analog behavioral modeling and other design verification teams, apply and advance existing and evolving Digital and AMS Verification methodologies and processes, and contribute to the entire life cycle of AMS Functional Verification process, from understanding specification, test planning to coverage closure and post silicon debugging support, to ensure High Quality and High Efficiency of Pre-Si Verification Delivery towards high quality silicon products.

Skills/Experience

Quick learner with strong critical thinking and creative problem-solving skills. Solid knowledge in ASIC design process, digital design, and UVM-based design verification methodologies.

Proficient on using design and verification languages: UVM, Verilog, System Verilog, and System Verilog Assertions (SVA). Proficient on Design Verification tools and techniques, including test bench development, simulation, debugging and coverage closure, etc. Knowledge on Design Verification development process, from specification to test plan, to configurable test bench, drivers and checkers development, to test suite building to meet functional and code coverage goals, 3+ years ASIC functional verification hands-on work experience, preferably with some verification experience on analog mixed signal IPs or SERDES IPs, such as USB, UFS, PCIe, DDR-PHY, etc. Power-aware simulations and gate level simulations is a plus

Scripting and automation skills: Unix/Linux shell programming, Perl, Python, Makefile, and revision management (e.g., Perforce, ClearCase, etc.) is a plus. Knowledge of Analog Mixed-Signal Design Fundamentals and analog behavioral modeling is a plus

Familiar with programming languages: C, C++, and/or SystemC is a plus.

Responsibilities

Work in AMS IP Design Verification, in UVM-based verification environment. Work in DV process from specification to test plan, to configurable test bench, drivers and checkers development, to test suite building to meet functional and code coverage goals. Apply wide range of Digital and/or AMS DV skills to help and support AMS IP or Chip DV Teams to establish or enhance new or existing DV capabilities, including but not limited to developing scalable and portable Test bench, test cases, drivers, checkers, assertions, and reference models, and running RTL and Gate Level simulations and reaching all coverage closures. Communicate and collaborate with global architecture, design, verification, and post-Silicon testing teams to address new needs or requirement on DV Support. Contribute to continuous improving on AMS DV process for better quality and efficiency through methodology and process improvements.