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AMD • Bengaluru, Karnataka, India
Role: SMTS Silicon Design Engineer (Senior individual contributor)
SystemVerilog, UVM-based verification, SystemVerilog Assertions (SVA)
IP verification across RTL, gate-level, analog/mixed-signal simulations
UPF-based low-power RTL verification; cosimulation (digital-analog)
Verification methodologies, code/functional coverage, assertion-driven flows
Verify IP features: create test plans; verify IP in RTL, gatesim, and analog/mixed-signal simulations
From-scratch development of UVM-based verification testbenches/components for various IP features
Ensure quality deliverables via regressions and achieve high verification coverage; participate in reviews with design/architecture teams
13+ years of experience; strong problem-solving and debugging
Expert in SystemVerilog, UVM-based verification, and SVA
Strong digital design knowledge; code and functional coverage expertise
Excellent communication and collaboration across sites/time zones
Experience with UPF low-power verification; digital-analog co-simulations desirable
Prior team leadership
PLL verification and mixed-signal verification methodologies
Exposure to cosims; experience with PLLs and mixed-signal verification
WHAT YOU DO AT AMD CHANGES EVERYTHING
At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.
SMTS SILICON DESIGN ENGINEER
The Role
The candidate will get to work on the Verification of complex PLLs that are delivered to various AMD SoCs.
You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience in collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.
Verification of IP features: Test plan creation, Verification of the IP in RTL, Gatesim and Analog Mixed Signal simulations. Create methodology-based (UVM) verification testbenches and components from scratch for various IP features. Quality deliverables through regressions
Verification coverage: code-coverage, functional coverage, assertions, to achieve 100% verification completeness Reviews, and feedback to design/architecture teams.
Years of experience 13+ Required. Expertise in System Verilog, methodology based testbench architectures such as UVM, and System Verilog assertions (SVA) Expertise in code and functional coverage. Excellent Problem solving and debugging skills. Excellent Communication skills Strong digital design knowledge. Exposure to UPF based low power RTL verification. Prior experience in leading a team is desirable. Prior experience in PLL verification and Mixed signal verification methodology is highly desirable. Exposure to digital-analog co-simulations (cosims) is desirable.
Bachelors or Masters degree in Electronics engineering/Electrical Engineering
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.
This posting is for an existing vacancy.
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