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Meta • Austin, Texas, United States
Role & seniority: ASIC Engineer (Infra Silicon Enablement) at Meta; mid-to-senior level (6+ years experience required)
Stack/tools: ASIC development lifecycle (pre/post silicon validation), Python, C/C++, emulation/FPGA platforms, Linux systems, server management; familiarity with PCIe, Networking/Ethernet, Flash/Memory, CPU/GPU, DRAM (LPDDR4/5, HBM), I2C, SPI, USB; RDMA/DPDK and host driver concepts are a plus
Lead end-to-end silicon validation strategy, planning, execution, and post-silicon enablement for product delivery
Develop validation plans, tests, and automation tools; perform silicon diagnostics, performance analysis, and full-stack/system validation from labs to data center deployments
Identify, diagnose, root-cause, and remediate silicon issues across the product lifecycle; provide feedback to next-gen architecture/design
6+ years in ASIC development cycles with Pre/Post Silicon Validation experience
6+ years in troubleshooting, debugging, and analytics for silicon products
Proficiency in Python and/or C/C++ and experience collaborating with internal/external ASIC and systems teams
Experience across ASIC design/development, emulation, and post-silicon validation
Experience with Emulation/FPGA for test content and enablement
Experience in PCIe, Networking/Ethernet, Flash, Memory, CPU/GPU, DRAM (LP/DDR4/5, HBM)
Embedded systems knowledge and familiarity with bu
Meta is hiring ASIC Engineers within the Infrastructure organization. We are looking for individuals with experience in the Pre/Post Silicon Validation to build and scale silicon for data center applications. As an ASIC Engineer in the Infra Silicon Enablement team, you will be part of a dynamic team working with the best in the industry, focused on developing and supporting innovative ASIC solutions for Meta’s data center applications.
Responsibilities
Work across all aspects of silicon lifecycle to deliver reliable and performant silicon solutions. From early architecture and design inputs, pre-silicon test readiness/validation, post-silicon bring-up, validation, characterization and deployment in fleet Create/develop validation plan, tests and automation tool sets targeted at silicon validation and productization. Inclusive of, but not limited to silicon diagnostics, performance analysis, debug tools, bare metal and full stack systems, from early labs to data center deployments Understand production system use cases to improve silicon validation Provide feedback into next generation architecture and design with insights from the production fleet Root-cause, resolve and remediate issues with silicon across the product lifecycle Lead end-to-end silicon validation effort, driving strategy, planning, execution, and post-silicon enablement to ensure successful product delivery
Minimum Qualifications
Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience 6+ years of experience with ASIC development cycles, Pre/Post Silicon Validation 6+ years of experience with troubleshooting, debug and analytics for Silicon products Experience in Python, C/C++ and/or similar languages (data structures, algorithms, and OOP) Experience working with internal and external partners for ASIC and/or systems development Experience in ASIC Design or Development, Emulation and Post Silicon validation
Preferred Qualifications
Experience working with Emulation/FPGA platforms for test content development, debug and enablement on post silicon
Experience with some of the following modules/domains: PCIe, Networking, Ethernet, Flash, Memory, CPU, GPU, DRAM (LP/DDR4/5 and/or HBM) Experience with Application, Host Driver development etc is plus Understanding of embedded systems, including common bus protocols such as I2C, SPI, USB, and/or PCIe Experience with Linux systems and server systems management Experience with RDMA Gen Driver, DPDK, Application, Host Driver development is a plus