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Lattice Semiconductor
Role & seniority: FPGA P&R Validation Engineer (mid-level) in a fast-paced, team-focused environment
Stack/tools: FPGA device families; P&R workflows; timing analysis; ECO flows; synthesis; constraint application; bitstream generation; regression suites; dashboards; scripting in Python, Tcl, Shell
Design and execute comprehensive test plans for FPGA P&R workflows (timing closure, optimization, ECO flows)
Validate functional correctness of P&R algorithms across device families; test options/configurations from a customer perspective
Automate test cases and maintain regression suites; provide data-driven validation reports; collaborate with P&R engineers
Strong FPGA P&R, timing closure, and ECO experience
Ability to simulate full design flows (synthesis, constraints, P&R, timing, bitstream)
Proficiency in scripting (Python, Tcl, Shell) for test automation; debugging timing reports and routing/resource issues
Experience with multiple FPGA device families; regression dashboards; QA/test automation in an hardware/software co-design context
Experience debugging ECO reliability and ECO application logs
Location & work type: Multiple international locations; full-time position with location-based work mode (on-site or hybrid as applicable)
Lattice Overview There is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality. Energy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for. Responsibilities & Skills
Simulate real-world design flows: synthesis, constraint application, P&R, timing analysis, and bitstream generation. Perform regression and stress testing for P&R and ECO features under complex design conditions. Automate test cases using scripting languages (Python, Tcl, Shell) for efficiency and scalability. Debug complex P&R and ECO issues by analyzing timing reports, routing congestion, ECO application logs, and resource utilization. Maintain regression suites and dashboards to monitor P&R performance, ECO stability, and timing closure success rates. Provide clear, data-driven reports on validation outcomes, functional correctness, and ECO reliability.