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Nextsi • Givatayim, Tel-Aviv District, Israel
Role & seniority: Senior Verification Engineer (lead verification from A to Z)
Stack/tools: SystemVerilog, UVM, Spaceman; Verilog/Verilog simulator; constrained random verification; functional and code/coverage; assertion methodology
Review specifications and develop attributes, tests, and coverage plans
Define methodology and test benches; build and maintain scalable verification environment
Work with verification, software, design, and micro-architecture teams to ensure product quality
5+ years of verification experience; hands-on in building complex environments from scratch
Advanced knowledge of verification flow, SOC architecture and design
Expertise in SystemVerilog, UVM, Spaceman; Verilog tools and debuggers
Constrained random verification, functional/Code coverage, assertions
BS in electrical engineering or computer science, or equivalent experience
Experience leading end-to-end verification efforts
HPC/AI domain exposure; ability to align verification with performance goals
Strong cross-functional collaboration and documentation skills
Location & work type: Location not specified; Work type not specified
NextSilicon is reimagining high-performance computing (HPC & AI). Our accelerated compute solutions leverage intelligent adaptive algorithms to vastly accelerate supercomputers, driving them forward into a new generation. We have developed a novel software-defined hardware architecture that is achieving significant advancements in both the HPC and AI domains.
Professionalism: We get exceptional results through professionalism and unwavering dedication to quality and performance.
Unity: Collaboration is key to success; we foster a work environment where every employee feels valued and heard.
Impact: We're passionate about developing technologies that make a meaningful impact on industries, communities, and individuals worldwide. We are looking for a talented and experienced engineer to take part in the verification efforts for the company’s core product. This position involves building a complex verification environment from scratch, and defining and executing a test plan. In this role, you will be leading verification from A to Z and will have a critical impact on the company.
Requirements 5+ years of verification experience, including hands-on experience building complex environments from scratch Advanced knowledge of verification flow, SOC architecture and design Expertise in verification languages such as SystemVerilog, UVM, Spaceman Knowledge of industry standard tools, including Verilog, Verilog simulator, and debug Clear understanding of constrained random verification process, functional coverage, code coverage, and assertion methodology and philosophy Bachelor degree in electrical engineering or computer science, or equivalent experience
Responsibilities Review specifications and develop attributes, tests, and coverage plans Define methodology and test benches Work closely with the verification team to ensure the quality of the product Build and maintain a smart and scalable verification environment that ties into various systems Work with the software, design, and micro-architecture teams to understand the functional and performance goals of the product’s design