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EnCharge AI • Santa Clara, California, United States
Role & seniority: Senior-level SOC validation engineer focused on post-silicon memory subsystem validation
Stack/tools: DDR memory subsystems (LPDDR4x/LPDDR5) on multiple SoC platforms; firmware for memory training (bootloaders, memory drivers, test hooks); RISC-V/ARM-based systems; C/C++ (low-level), Python/Perl; lab equipment (oscilloscopes, logic analyzers, BERTs, power analyzers); silicon bring-up tools (Lauterbach, JTAG, trace analyzers); embedded OS and boot sequences
Lead validation of LPDDR4x/LPDDR5 memory subsystems across SoCs, defining and executing test plans (training, performance, stress, timing margins, reliability)
Develop, integrate, and debug memory-training firmware; implement necessary components for testing; ensure correct hardware–software interactions
Automate validation workflows and perform root-cause analyses, coordinating with hardware, firmware, software, SI/PI teams
10+ years SOC validation experience; 5+ years post-silicon memory-subsystem validation (LPDDR4x/LPDDR5)
Strong C/C++ for low-level code and hardware bring-up; proven firmware integration/debugging in memory validation or SoC contexts
Deep DRAM knowledge: memory controller architecture, JEDEC LPDDR standards, timing parameters
Silicon bring-up experience and tools (Lauterbach, JTAG, trace analyzers); embedded OS and boot sequences; system-level memory performance tuning
EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge’s robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today’s best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI systems. About the Role This is a senior-level engineering position focused on the post-silicon validation of memory subsystems within System-on-Chip (SoC) products. The role demands a strong combination of hardware validation skills, particularly in memory systems, and significant hands-on experience in developing, integrating, and debugging low-level firmware specifically for memory training and testing purposes. The engineer will be responsible for the entire validation cycle, from planning and execution to automation, debugging, and reporting, working closely with various hardware, firmware, and software teams. Responsibilities Take lead responsibility for validating DDR memory subsystems (LPDDR4x, LPDDR5x) on multiple SoC platforms. Define comprehensive test plans and execute tests covering memory training procedures, performance benchmarks, stress scenarios, timing margin analysis, and overall reliability. Collaborate with design and firmware teams to develop, integrate, and debug firmware essential for memory training. Write necessary firmware components (like bootloaders, memory drivers, test hooks) to enable testing. Integrate and debug firmware for memory initialization and training, specifically on systems using RISC-V or ARM processors. Work closely with software and hardware teams to ensure firmware and hardware components interact correctly. Coordinate with board and Signal/Power Integrity (SI/PI) teams for related evaluations. Utilize standard lab equipment (oscilloscopes, logic analyzers, BERTs, power analyzers) for test execution, data collection, and troubleshooting memory-related issues. Perform root cause analysis for failures. Develop scripts (Python, Perl, C/C++) to automate test procedures and validation workflows. Qualifications BSEE/BSCE or equivalent experience 10+ years of SOC validation experience At least 5 years of experience in post-silicon Memory subsystem validation, with a specific focus on LPDDR4x or LPDDR5 memory subsystems. Strong C/C++ programming skills, particularly for low-level code (like hardware abstraction layers) used in system bring-up. Proven experience integrating and debugging firmware in memory validation or general SoC environments. Deep understanding of DRAM operations, memory controller architecture, standard memory training algorithms, and JEDEC LPDDR standards (including timing parameters). Experience with silicon bring-up processes and associated tools like Lauterbach debuggers, JTAG interfaces, and trace analyzers. Familiarity with embedded operating systems and the typical boot sequences. System-level memory performance tuning and characterization.