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Software Placements • Cork, Munster, Ireland
Role & seniority: Principal Digital Design Verification Engineer (SERDES)
Location & work type: Cork City, Ireland; full-time role; cross-timezone collaboration with US teams
High-speed SERDES / PHY verification at 112 Gbps+; 3nm FinFET CMOS
Protocols: PCIe (Gen 7), UCIe, Ethernet
Digital design & verification: Verilog, SystemVerilog, UVM
Formal verification (Assertion Based); LINT, Synthesis, CDC Analysis; RTL verification
Prototyping, Emulation, customer delivery; cross-functional collaboration
Verify high-speed SERDES/PHY IP up to and beyond 112 Gbps on advanced nodes
Specification, design, and verification of high-speed PHY IP per PCIe, Ethernet; drive coverage-based verification and closure
Technical leadership within the verification team; prototyping, emulation, customer support; coordinate with architecture, RTL, layout, and test teams
≥7 years in CMOS SERDES or high-speed IO design/verification
RTL: Verilog; verification: SystemVerilog + UVM
Assertion-based formal verification; front-end tools (LINT, Synthesis, CDC Analysis)
Strong problem-solving, communication, and stakeholder management
Post-silicon validation and customer IP deployment experience
Knowledge of PCIe, CXL protocols; prior SERDES/IP deployment experience
Our client a leading Multinational Semiconductor EDA Software provider has an opening for Principal Digital Design Verification Engineer (SerDes) for role based in Cork City, Ireland.
As Principal Verification Engineer (SerDes) you will take a Technical Leadership role on the Verification team (Digital & AMS) as part of a SERDES Product Team located at Cork, Ireland.
You will be working on the leading edge of Wireline technology at the highest data rates (112Gbps+) and on the smallest technology nodes (e.g. 3nm).
The PHY team designs products for communication protocols such as PCIe (now at Gen 7) and UCIe (emerging Chiplets standard).
Verification of High Speed SERDES products at data rates up to and exceeding 112 Gbps on leading edge technology nodes (e.g. 3nm FinFET CMOS) Specification, Design and Verification of High Speed PHY IP based on communication protocols (PCIe, Ethernet) Verification from initial concept/specification through final verification of conformance to customer specifications using Coverage metric Implementation, Tracking and Closure Prototyping, Emulation, Customer delivery and support Work with cross-functional teams ranging from architecture, all aspects of circuit design, Layout development, RTL design & Validation, Physical design & Test chip development Participate in technical leadership of the team in the areas of digital design and verification, SERDES architectures Work with global teams (US, west coast and east coast), which work in different time-zones
BEng, MEng, PhD or equivalent
Candidate’s background should include a minimum of 7 years of experience in CMOS SERDES or high-speed I/O IC design and development Working knowledge of a set of common SERDES standards Wide experience with digital design and verification tools; RTL design using Verilog & verification with System Verilog and UVM Experience of Assertion Based Formal Verification essential Experience of Front-end design tools covering LINT, Synthesis & CDC Analysis Excellent problem-solving skills and ability to work cooperatively in a team environment Excellent communication and stakeholder management skills
Prior experience with post Silicon validation & customer IP deployment of one or more Serial IO IPs/ complex Memory Interface IPs is an added advantage Knowledge of PCIe, CXL protocols preferred
For further information please contact Mícheál at Software Placements on 00353 1 5254642 or email micheal@softwareplacements.ie