Full Description

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Job Title: Lead – SoC/Sub-System Design Verification

Location: Sunnyvale, CA (Onsite)

Job Summary

We are seeking an experienced and highly motivated Lead Engineer to drive the design verification of complex System-on-Chip (SoC) and sub-system architectures. The ideal candidate will lead a team of verification engineers, define verification strategies, and ensure the delivery of high-quality silicon through comprehensive verification planning, execution, and closure.

Key Responsibilities

Lead the verification planning and execution for SoC and sub-system designs, ensuring coverage of functional, performance, and reliability requirements. Define and implement verification methodologies (UVM/OVM, SystemVerilog, or equivalent) for RTL and IP verification. Develop and maintain testbenches, simulation environments, and verification tools to validate complex designs. Collaborate with architecture, RTL design, and validation teams to identify potential design risks and provide timely feedback. Mentor and manage a team of verification engineers, including resource allocation, technical guidance, and career development. Review verification results, analyze failures, debug design issues, and propose corrective actions in collaboration with RTL designers. Drive automation and process improvements to enhance verification efficiency and quality. Coordinate with cross-functional teams to ensure schedule adherence and deliverables quality. Maintain thorough documentation of verification plans, test results, and coverage metrics. Stay updated on industry best practices and emerging verification tools and methodologies.

Required Qualifications

Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field. 8+ years of experience in SoC or sub-system verification, with 3+ years in a lead or technical lead role. Strong experience with SystemVerilog, UVM/OVM, or similar verification frameworks. Proven track record in developing verification plans, testbenches, and directed/random test scenarios. Hands-on experience with simulation, emulation, or FPGA-based verification. Strong understanding of SoC architectures, including processor cores, memory subsystems, interconnects, and peripheral IPs. Excellent debugging, analytical, and problem-solving skills. Strong leadership and mentoring skills, with the ability to drive a team toward delivery. Effective communication skills for cross-functional collaboration.

Preferred Qualifications

Experience with formal verification, assertion-based verification, and coverage-driven methodologies. Familiarity with low-power design, DV methodology for mixed-signal SoCs, or hardware/software co-verification. Exposure to high-speed interfaces such as PCIe, USB, DDR, or Ethernet. Familiarity with script-based automation using Python, Perl, or TCL.