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Lead IP/SOC Verification at AMD - QATestingJobs.com
A
Lead IP/SOC Verification
AMD • Folsom, California, United States
hybridfull-time
Salary: USD 0 per year
Posted Dec 17, 2025Apply by Dec 17, 2026
Role & seniority: Lead IP/SOC Verification; senior/lead verification role for next‑gen graphics program; potential progression toward technical leadership.
Own and lead verification quality for GFXIP projects; define features, verification and execution plans.
Develop verification strategy, infrastructure, and test plans; drive pre- and post-Si verification closure to meet schedule with quality.
Collaborate with architects, hardware, firmware teams; drive triage post-Si; automate workflows; guide domain leads to improve quality and verification outcomes.
Must-have skills
Proven technical leadership in IP/SoC verification; multiple ASICs in production.
Strong experience with UVM, SystemVerilog, C/C++, scripting; coverage-driven verification and assertion-based techniques.
Familiarity with state-of-the-art verification methods, ISA knowledge a plus; gate-level, power and reset verification.
Nice-to-haves
Graphics-domain experience; processor-based SoC verification; experience with Agile, JIRA, Confluence; experience driving verification closure and program delivery.
Location & work type: Hybrid work arrangement; not specified location. Not eligible for visa sponsorship.
Full Description
WHAT YOU DO AT AMD CHANGES EVERYTHING
At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.
THE ROLE
In this high-profile role, the Lead IP/SOC Verification will be the overall design verification lead for next generation graphics program. You will work across all of engineering and business to meet overall verification needs
THE PERSON
A successful candidate will work with senior silicon design engineers. The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills.
Good understanding of requirements management, documentation management, and defect management
Ability to grasp concepts during discussions and turn minutes into action items
Able to communicate concepts and processes with stakeholders
Analytical, self-motivated, organized, detailed-oriented and results-oriented
Excellent interpersonal skills including the ability to work well with multiple people and teams, ability to communicate progress to team members on a regular basis
Experience working in a high-pressure environment and competing priorities and tight turnaround times
KEY RESPONSIBLITIES
Closely work with designers and architect to come up with features, verification and execution plans
Own and lead verification quality for GFXIP projects
Engage with IP and SOC teams to drive closure to verification strategy
Working with architects and verification leads and driving quality test plan specifications.
Collaborate with architects, hardware engineers, and firmware engineers to understand the complex features and impact to System level/SOC environment
Developing verification strategy, infrastructure and needed improvements
Driving Pre and post Si verification closure to meet schedule with quality
Leading Post Si verification activities to drive triage with FW, SW, IP, SOC and various teams. Plug holes appropriately to improve quality of the IP
Working with each domain (sub-system) lead and guide them to get better quality and verification outcome
IP VerificationSOC VerificationUVMSystemVerilogC/C++Scripting LanguagesVerification TechniquesCode CoverageFunctional CoverageAgile MethodologyJIRAConfluenceGraphics DomainProcessor Based SoC VerificationGate Level SimulationPower Verificationmulti-location
Automating workflows in a distributed compute environment
Helping management with risk assessment on features, quality, and schedules
This individual will work with engineering management to drive execution excellence, including key metrics - performance, schedule, cost, quality
Plan, Execute, Verify and Track new features at IP and SoC level
Desire and enthusiasm to grow into leadership role taking progressive responsibility over time
Aspiration to grow to technical lead responsible for project level design verification
Defines, plans and drives projects and program plans based on management and senior technical guidance
Possesses specialized knowledge plus a broader technical knowledge in areas outside his or her area of expertise
Has responsibility for projects or processes of significant technical importance and for results that cross engineering project areas
Initiates significant changes to existing processes and methods to improve project and team efficiencies
PREFERRED EXPERIENCE
Experience focused on IP and/or SOC verification with successful completion of multiple ASICs that are in production
Prior experience in Graphics domain is highly beneficial, though not a requirement
Requires proven track record in technical leadership. This includes planning, execution, tracking, verification closure, and delivery to programs.
Requires strong experience with development of UVM, SystemVerilog, C/C++ and Scripting Languages
Requires strong understanding of state of the art of verification techniques, including assertion and metric-driven verification
Good understanding of code and functional coverage, ability to influence coverage improvement with design and verification teams
Experience with Processor based SoC verification and understanding of at least one ISA is a plus
Experience with gate level simulation, power verification, reset verification, abstraction techniques is a plus
Experience with Agile methodology, JIRA and Confluence
ACADEMIC CREDENTIALS
Undergrad degree required. Bachelor, Master's or PhD degree in Electrical or Computer Engineering preferred.
This role is not eligible for Visa sponsorship.
#LI-BM1
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Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
