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AMD • San Jose, California, United States
Salary: USD 136,000–204,000 per year
Role & seniority: Senior Silicon Design Verification Engineer (AECG)
Stack/tools: High-speed IP verification (Crypto, NoC, memory controllers for LPDDR6/DDR5, HBM4); IP & SoC-level verification; UVM, SystemVerilog testbenches; formal verification and assertion-based verification; simulation tools (Synopsys VCS, Cadence Xcelium); verification management and regression tools; familiarity with VC Formal/JasperGold/Questa Formal a-plus.
Lead verification of high-speed Crypto, NoC, and DRAM memory controller designs; ensure quality and performance.
Architect, develop, and maintain verification environments and testbenches at IP and SoC levels; create and execute verification plans.
Lead and manage verification teams (planning, execution, tracking, closure, delivery) and collaborate with design, architecture, and software teams; mentor junior engineers.
Proven technical leadership of verification teams (5+ engineers) and track record delivering verification for NoC, crossbar, and system-level QoS requirements.
Expertise in UVM, SystemVerilog test benches; experience with simulation/debug tools (VCS, Xcelium).
Strong knowledge of modern verification methodologies (assertion-based, coverage-driven, formal verification); experience as a verification architect is a plus.
Familiarity with regression management and verification databases; BS/MS/PhD in EE/CE/CS.
WHAT YOU DO AT AMD CHANGES EVERYTHING
At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.
The Role
Adaptive and Embedded Computing Group (AECG) seeks a Senior Silicon Design Verification Engineer to provide technical leadership and expertise in the verification of high-speed Crypto, Network-on-Chip (NoC), and cutting-edge DRAM Memory Controller IPs (LPDDR6, HBM4). You will be responsible for architecting, developing, and utilizing simulation and/or formal-based verification environments at both block and SoC-level to achieve first-pass silicon success.
The Person
The ideal candidate has a proven track record in driving strategies and successfully executing verification strategies for Pre-Silicon Design IP and/or SOC designs. They should be strong team players with excellent communication and leadership skills, capable of positively and strategically influencing design teams to improve overall product quality.
Key Responsibilities
Lead the verification of high-speed Crypto, Network-on-Chip (NoC), cutting-edge DRAM Memory controller (LPDDR6, DDR5) designs, ensuring the highest standards of quality and performance. Architect, develop, and use simulation and/or formal-based verification environments at IP and SoC-level. Lead and manage verification teams, including planning, execution, tracking, verification closure, and delivery to programs. Develop and execute comprehensive verification plans, including testbenches and test cases. Collaborate with design, architecture, and software teams to define and implement verification strategies. Utilize advanced verification methodologies, including UVM, formal verification, and assertion-based verification. Mentor and guide junior engineers, fostering a collaborative and innovative team environment.
Preferred Experience
Proven track record in technical leadership of teams with 5+ engineers. This includes planning, execution, tracking, verification closure, and delivery to programs. Proven track record on driving strategies and successful verification execution of NoC, Crossbar switches, analyzed and verified system-level Performance and QoS (Quality of Service) requirements. Experience with development of UVM and System Verilog test benches and usage of simulation tools/debug environments such as Synopsys VCS or Cadence Xcelium. Require strong understanding of state of the art of verification techniques, including assertion and coverage-driven verification. Experience as a verification architect, establishing the verification methodology, tools and infrastructure for high-performance IP and/or VLSI designs is a plus. Familiarity with verification management tools as well as an understanding of database management particularly as it pertains to regression management. Experience with formal property checking tools such as VC Formal (Synopsys), JasperGold (Cadence), and Questa Formal (Mentor) is a plus. Experience with gate-level simulation, power-aware verification is a plus. Experience with silicon debug at the tester and board level, is a plus.
Academic Credentials
BS, MS or PhD in Electrical Engineering, Computer Engineering or Computer Science.
This role is not eligible for visa sponsorship.
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.