Role & seniority: Design Verification Engineer; seniority not explicitly stated (key contributor / mid-to-senior level implied)

Stack/tools: SystemVerilog, UVM (or OVM/VMM), Verilog testbenches; constrained-random and directed verification; SystemVerilog Assertions (SVA); formal tools (Cadence IEV, Jasper, Synopsys VC-Formal/Magellan); simulation/debug tools (Synopsys VCS, Cadence IES); experience with AXI3/4, DDR4/5, HBM, PCIe, NOC/SoC/FPGA contexts

Top 3 responsibilities

Plan verification for complex digital designs; translate architecture/design specs into a test plan
Design and maintain testbenches in SystemVerilog/UVM; develop constrained-random and formal verification environments
Debug with design engineers; perform coverage analysis and drive closure of verification coverage

Must-have skills

Proficiency with UVM/SystemVerilog testbenches; strong verification methodology and debugging capabilities
Experience across ASIC/full-chip/SoC verification, block-level verification, and understanding of verification phases
Ability to write/testbench-based coverage metrics and use formal verification tools

Nice-to-haves

Verification architect experience; establishing methodologies/infrastructure for high-performance FPGAs/SoCs
Experience with gate-level, power/reset verification, abstraction techniques; NOC verification
Familiarity with regression management and verification databases; protocol expertise (AXI, DDR, PCIe, HBM)
Loc

Full Description

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.

THE ROLE

We are looking for an adaptive, self-motivative design verification engineer to join our growing team. As a key contributor, you will be part of a leading team to drive and improve AMD's abilities to deliver the highest quality, industry-leading technologies to market. The Verification Engineering team furthers and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development.

THE PERSON

You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/time zones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.

KEY RESPONSIBILITIES

Plan verification of complex digital design blocks by fully understanding the architecture and design specifications
Interact with architects and design engineers to create a comprehensive verification test plan
Design testbenches in System Verilog and UVM to complete verification of the design in an efficient manner
Create and enhance constrained-random and/or directed verification environments, and formally verify designs with System Verilog Assertions (SVA) and industry leading formal tools
Debug tests with design engineers to deliver functionally correct design blocks
Identify and write coverage measures for stimulus quality improvements
Perform coverage analysis to identify verification holes and achieve closure on coverage metrics

PREFERRED EXPERIENCE

Experienced with development of UVM, OVM, VMM and/or System Verilog, Verilog test benches and usage of simulation tools/debug environments like Synopsys VCS, Cadence IES to test block level/full chip SOCs and FPGAs.
Strong understanding of state of the art of verification techniques, including assertion and coverage-driven verification.

Silicon Design Verification Engineer