Role & seniority: Design Verification Engineer (mid-to-senior level)

Stack/tools: SystemVerilog, UVM, constrained-random/directed verification, SystemVerilog Assertions (SVA); simulation/tools: Synopsys VCS, Cadence IES; Verilog/OVM/VM M; formal tools (IEV, Jasper, Synopsys VC-Formal, Magellan); experience with ASIC/SoC/block-level/FPGA environments

Top 3 responsibilities

Plan verification for complex digital design blocks by understanding architecture and specs
Design and maintain testbenches, verification environments, and coverage plans; debug with design engineers
Develop/enhance constrained-random and/or directed verification, perform coverage analysis, and aim for closure on coverage metrics
Must-have skills: strong SystemVerilog/Verilog, UVM experience, ability to verify ASIC/SoC blocks, debug and collaboration across teams/time zones, familiarity with verification planning and coverage-driven methodologies
Nice-to-haves: formal verification tools (SVA, IEV, Jasper, Magellan, VC-Formal), experience with gate-level/soc-level verification, familiarity with protocols (AXI3/4, DDR4/5, PCIe, HBM), NOC verification, verification architect experience, regression management and tool/infrastructure setup
Location & work type: San Jose, CA; Hybrid work arrangement; not eligible for visa sponsorship; full-time role

Full Description

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.

THE ROLE

We are looking for an adaptive, self-motivative design verification engineer to join our growing team. As a key contributor, you will be part of a leading team to drive and improve AMD's abilities to deliver the highest quality, industry-leading technologies to market. The Verification Engineering team furthers and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development.

THE PERSON

You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/time zones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.

KEY RESPONSIBILITIES

Plan verification of complex digital design blocks by fully understanding the architecture and design specifications
Interact with architects and design engineers to create a comprehensive verification test plan
Design testbenches in System Verilog and UVM to complete verification of the design in an efficient manner
Create and enhance constrained-random and/or directed verification environments, and formally verify designs with System Verilog Assertions (SVA) and industry leading formal tools
Debug tests with design engineers to deliver functionally correct design blocks
Identify and write coverage measures for stimulus quality improvements
Perform coverage analysis to identify verification holes and achieve closure on coverage metrics

PREFERRED EXPERIENCE

Experienced with development of UVM, OVM, VMM and/or System Verilog, Verilog test benches and usage of simulation tools/debug environments like Synopsys VCS, Cadence IES to test block level/full chip SOCs and FPGAs.
Strong understanding of state of the art of verification techniques, including assertion and coverage-driven verification.
Strong understanding of different phases of ASIC and/or full custom chip development is required.
Experience in block level NOC (Net work on Chip) verification is a plus.
Verification Experience in protocols like AXI3/4, DDR4/5, HBM, PCIe, Processors, Graphics is a plus.
Experience as a verification architect, establishing the verification methodology, tools and infrastructure for high performance FPGAs, SOCs and/or VLSI designs is a plus.
Experience with gate level simulation, power verification, reset verification, contention checking, abstraction techniques is a plus.
Familiarity with verification management tools as well as understanding of database management particularly as it pertains to regression management is a plus.
Experience with formal property checking tools such as Cadence (IEV), Jasper and Synopsys (VC-Formal, Magellan) is a plus.

ACADEMIC CREDENTIALS

Bachelors or Masters degree in Computer Engineering/Electrical Engineering

LOCATION: San Jose, CA #LI-DW1 #LI-HYBRID This role is not eligible for visa sponsorship.

Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.

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