Full Description

About Us Axelera AI is not your regular deep-tech startup. We are creating the next-generation AI platform to support anyone who wants to help advancing humanity and improve the world around us. In just four years, we have raised a total of $120 million and have built a world-class team of 220+ employees (including 49+ PhDs with more than 40,000 citations), both remotely from 17 different countries and with offices in Belgium, France, Switzerland, Italy, the UK, headquartered at the High Tech Campus in Eindhoven, Netherlands. We have also launched our Metis™ AI Platform, which achieves a 3-5x increase in efficiency and performance, and have visibility into a strong business pipeline exceeding $100 million. Our unwavering commitment to innovation has firmly established us as a global industry pioneer. Are you up for the challenge? Position Overview As a Verification Engineer at Axelera AI, you will join a team responsible for the verification of in-house designed, complex, multi-market AI accelerators. Your role will be critical in achieving the highest level of quality and performance in our products. This is an opportunity to work with cutting-edge technology and a dedicated team of professionals who share your passion for pushing the boundaries of what's possible. We are open to a range of experience levels for this opportunity.

Key responsibilities

• Guarantee RTL designs are matching specifications and requirements.
• Define, implement and execute verification plans to ensure the designs meet quality and performance goals.
• Build and maintain automated verification environments.
• Collaborate and communicate regarding verification status, project progress, and issue resolution.
• Work closely with designers, architects and software engineers to develop effective and pragmatic approaches to complex problems.
• Contribute to technical directions on all aspects of the verification domain.
• Qualifications/Skills

Education: A degree in electronics engineering, electrical engineering, computer science or other relevant discipline.

Experience: A minimum of 3 years of experience in ASIC or FPGA verification. Experience with emulation is an advantage.

Verification Expertise: Proficiency in SystemVerilog, C/C++ or Python for designing and implementing testbenches. Experience with commercial simulation and formal verification tools and in UVM or CocoTB is an advantage.

Scripting: Proficiency in scripting languages such as Python, shell or Tcl for automation.

Collaboration / Team Player: Demonstrated ability to work closely with architecture, RTL design, and software teams to ensure comprehensive verification coverage.