Graphics Cache Hierarchy Design Verification Engineer
Apple • Santa Clara, California, United States
Role & seniority: Graphics Cache Hierarchy Verification Engineer (mid-level equivalent; BS + 3+ years)
Stack/tools: CPU/GPU architecture experience; HDL (VHDL/Verilog); SystemVerilog; HDL simulators; waveform viewers; UVM; portable verification test benches; scripting (Perl, Ruby, Shell); Makefiles
Top 3 responsibilities
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Develop verification plans with design leads/architects; create automated verification flows
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Build/maintain portable test benches and environments; generate directed and constrained random tests
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Run simulations, debug designs/environments, create functional coverage, analyze/close coverage holes
Must-have skills
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Experience in CPU or GPU architecture
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Experience developing unit or cluster-level test environments; bring-up and debug of complex designs
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Proficiency with SystemVerilog and HDL simulators; familiarity with verification methodologies (e.g., UVM)
Nice-to-haves
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Software/programming skills; cache verification and memory subsystem testing
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Understanding of Graphics Pipeline
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Experience defining unit test plans, coverage space/closure
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Scripting: Perl, Ruby, Shell; Makefiles
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Location & work type: Location not specified; remote/on-site/work arrangement not provided in posting
Full Description
Do you love creating elegant solutions to highly complex challenges? As part of our Silicon Technologies group, you’ll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You’ll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. Joining this group means you’ll be responsible for crafting and building the technology that fuels Apple’s devices. Together, you and your team will enable our customers to do all the things they love with their devices. The Graphics Cache Hierarchy Verification Engineer will be responsible for the pre-silicon RTL verification of graphics memory subsystem units including Caches, Memory Management Unit, Interconnects and Link interface units. This includes deep understanding of the micro-architectural details of their block and how it works within the broader GPU design. A strong computer architecture background, and a solid foundation in verification methodology is required.
DESCRIPTION
In this role you will: - Develop verification plans in coordination with design leads and architects. - Build and maintain portable verification test bench components and environments. - Generate directed and constrained random tests. - Run simulations and debug design and environment issues. - Create functional coverage points, analyze coverage, and improve test environment to target coverage holes. - Create automated verification flows for block verification. - Apply knowledge of hardware description languages (VHDL/Verilog) to verify complex designs. - Work with other block, memory subsystem and core level engineers to ensure seamless verification flow.
MINIMUM QUALIFICATIONS
Experience in CPU or GPU architecture. Experience developing unit or cluster level test environments. Experience with driving bring up and debug of complex designs. Experience with verification languages such as SystemVerilog. Experience with HDL simulators and waveform viewers. BS + minimum of 3 years of experience.
PREFERRED QUALIFICATIONS
Strong fundamental software and programming skills. Experience with cache verification and memory subsystem testing highly desired. Understanding of the Graphics Pipeline a plus. Experience defining and executing unit level test plans. Experience with common verification methodologies such as UVM. Experience defining coverage space, writing coverage and coverage closure. Experience with Perl, Ruby, Shell scripting, Makefiles.
