Role & seniority: Silicon Design Verification Engineer ( focused on IP verification ) within AMD’s Data Accelerator (DACC) team.

Stack / tools: Verilog, SystemVerilog, UVM; Linux and Windows environments; Makefiles; scripting languages (Python, Perl, Ruby); formal verification techniques; AI-assisted verification workflows; emulation support.

Top 3 responsibilities

Develop and maintain block-level IP verification testbenches, test methodology, and infrastructure; create detailed test plans for new features.
Triage regressions, debug simulations, analyze coverage, and drive verification closure across design, verification, and other teams.
Apply verification methodologies (UVM, formal verification), reproduce silicon functional bugs in simulations/tools, and participate in code reviews.

Must-have skills

Proficiency in Verilog/SystemVerilog; experience with UVM; strong debugging of RTL in simulation.
Linux/Windows fluency; scripting and automation (Makefiles, Python, Perl, etc.); excellent programming skills.
Ability to work across sites/time zones; strong analytical/problem-solving capabilities.

Nice-to-haves

Familiarity with formal verification and AI techniques for verification.
Experience with power and performance verification (PPV) and emulation workflows.
Location & work type: Markham, Ontario, Canada; hybrid work arrangement.

Full Description

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.

THE ROLE

The Data Accelerator (DACC) team at AMD is seeking an Silicon Design Verification Engineer who will be involved in multiple aspects of IP verification. This role is an excellent opportunity to work on next generation technologies that are part of AMD's products powering Servers, Datacenters, Client and Embedded markets. You will join one of the fastest-growing areas of adding custom hardware offload engines to support complex operations like encryption, authentication, compression, GPU/CPU compute offloads & virtual machines live migration. This is a tremendous opportunity to get in early into the rapidly expanding domain of custom hardware accelerators. The Design Verification (DV) group within this team is responsible for developing a scalable DV flow and environment with emphasis on automation (using AI), power and performance verification (PPV) and emulation support. Our management fosters and encourages continuous technical innovation to showcase success as well as continuous career development.

THE PERSON

You have a passion for modern functional verification techniques and are eager to learn new designs and implementation methodologies. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.

KEY RESPONSIBILITIES

Develop and maintain block level IP verification testbenches, test methodology and infrastructure
Develop detailed test plans for covering new features
Triage regressions, debug simulations, analyze coverage, work/resolve technical issues with design, verification and other teams to achieve verification closure
Deploy industry leading verification methodologies such as UVM and formal verification
Reproduce silicon functional bugs in simulations and/or formal verification tools
Conduct and participate in code reviews

Design Verification Engineer