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Apple • San Diego, California, United States
Role & seniority: SoC DRAM Memory Subsystem Validation and Debug Program Manager (senior program/lead level)
Stack/tools: SoC memory architecture; DRAM devices; high-performance memory subsystems; DDR controller and PHY; validation, debug, and software interfaces; cross-functional interaction with DRAM architecture, Memory Controller DV, DDR PHY, DRAM product engineering
Drive memory subsystem readiness for custom Apple SoCs: bring-up, validation, and complex debug of the memory subsystem
Help craft the DRAM industry mobile roadmap and drive innovative DRAM technologies across product lines
Act as the interface between DRAM architecture, Memory Controller DV, PHY, DRAM product engineering, and software teams to ensure delivery from architecture to mass production with Apple quality standards
BS + 10 years in SOC DRAM memory design, validation, architecture, or test/product engineering
Knowledge of high-performance memory subsystems, SoC memory architecture, DDR controller/PHY, DRAM devices, and calibration/training
Experience shipping high-volume DRAMs/SoCs; ability to manage multi-disciplinary teams; strong debugging and crisis-management capabilities; ability to extract action plans from complex discussions; ability to report succinctly to executives
Experience with DRAM vendors and DRAM device validation
Track record of driving project development with metrics in a dynamic, s
Come and join the team that crafts Apple's groundbreaking silicon. Apple makes the greatest SoCs in the world; to do that takes thousands of employees, multiple years, and very significant R&D spending. To make the best use of those employees, time and money requires excellent methodologies and structures. As we continue to expand and mature, the processes used to develop these SOCs must be improved. Join us to do your life’s best work in this rare opportunity to help define the next big thing that will surprise and delight the world!
DESCRIPTION
The SoC DRAM Memory Subsystem Validation and Debug Program Manager will drive the memory subsystem readiness for our custom SoCs. Our high-bandwidth multi-client memory subsystems are blazing new territory with every generation. The charter will include managing bring-up, validation, and the complicated debug of our groundbreaking memory subsystem. The EPM will also help craft the DRAM industry’s mobile roadmap and drive innovative DRAM technologies to accompany SoC’s across Apple’s product lines. In this multifaceted role, you will be the critical interface between Apple’s DRAM architecture, Memory Controller Design and DV, DDR PHY, DRAM product engineering, and software teams to ensure these sophisticated memory technologies are delivered from architecture to mass production to Apple’s industry leading quality standards.
MINIMUM QUALIFICATIONS
BS + 10 years of relevant experience Prior experience in SOC DRAM Memory Design, Validation, Architecture or Test/Product Engineering.
PREFERRED QUALIFICATIONS
Knowledge of high-performance memory subsystem, including SoC memory architecture, sophisticated DDR controller, PHY design and high-speed IO interface, DRAM device, and associated calibration/training mechanisms. Experience shipping high volume DRAMs / SoCs. Previous experience working with major DRAM memory vendors and validation of DRAM device is also a plus. Experience working in a high-energy multi-disciplined engineering environment, strong at multi-tasking, and real-time crisis management. Excellent debugging skills. Proven track record to drive resolution of critical problems, while under pressure. Ability to understand complex technical discussions and extract action plans. Passionate to own/drive project development using well-defined metrics. Thrives in dynamic schedule driven development environment. Ability to succinctly summarize complex details for executive reporting. Extraordinary leadership skills and ability to encourage team members with a dedication to see the bigger picture Phenomenal leadership and social skills with a reciprocal approach.